TDECQ Explained: How to Interpret PAM4 Transmitter Quality from 100G to 800G

1. What TDECQ Actually Measures

Every PAM4 transmitter is compared, in a lab, to an ideal reference transmitter. TDECQ is how much worse the real one is, in decibels. A perfect transmitter scores 0 dB. A transmitter at the IEEE ceiling scores 3.4 dB. Everything between those numbers is margin — reserve the link keeps for the connector that's dirtier than expected, the patch panel that added an insertion loss nobody planned for, or the summer afternoon when the chiller is working harder than usual.

"Worse" is defined precisely: simulated noise is added to the transmitter's output until the link reaches a symbol error rate of 4.8 × 10^-4 — the edge of the FEC cliff, where the Reed-Solomon error correction every PAM4 link depends on is just barely still working. The amount of noise the real transmitter tolerates, compared to an ideal one, is the TDECQ penalty. Lower is better.

This replaced the older NRZ-era method of dropping a polygon "eye mask" over the eye diagram and passing if no traffic fell inside. PAM4 eyes are physically closed before equalization — every mask-based test would fail every module. TDECQ sidesteps that by measuring what an equalized receiver actually sees, which is what every Marvell, Broadcom, and Credo DSP is doing in silicon anyway.

2. Inside the Measurement: Five Stages, One Number

The test itself is standardized tightly. You don't need to run it — your module vendor does — but understanding the shape of it makes the datasheet much easier to read.

Stage 1 — the transmitter sends a standardized stress pattern called SSPRQ: 65,535 symbols long, specifically designed to reproduce the worst-case baseline wander real network traffic produces. A shorter pattern called PRBS13Q (8,191 symbols) exists too and is easier to pass, so IEEE is specific about which one counts.

Stage 2 — the reference filter. The signal passes through a 4th-order Bessel-Thomson filter set to half the symbol rate: 26.56 GHz for 100G-PAM4, 53.13 GHz for 200G-PAM4. This simulates a real receiver's front end. It intentionally closes the eyes, because real receivers have limited bandwidth too.

Stage 3 — the virtual equalizer. A feed-forward equalizer reopens the closed eyes. For current standards (100G through 800G), it's a 5-tap FFE. For the upcoming 802.3dj standard (800G at 200G per lane, 1.6T), it's a 15-tap FFE plus a 1-tap DFE. The equalizer taps are optimized to give this specific transmitter its best-case receiver performance — not to help it cheat, but to match what modern receive DSPs actually do in silicon.

Stage 4 — the histograms. Eight vertical histograms are captured across the three PAM4 eye crossings at two time positions (0.45 UI and 0.55 UI). These capture the actual signal distribution at each sub-eye.

Stage 5 — the penalty. Simulated Gaussian noise is added until measured SER hits 4.8 × 10^-4. The same process runs against an ideal reference. The difference in noise tolerance, in dB, is the TDECQ value. That's the number on the datasheet.

3. The Hidden Decibels: IEEE vs Hyperscaler Specs

If every module passing at 3.4 dB were equally good, the operators running the largest AI data centers in the world wouldn't bother specifying tighter. They do, and their numbers are public.

The reason the gap exists is that IEEE writes ceilings — the worst the industry will tolerate while still calling a module compliant. That's the right job for a standards body. Hyperscalers running AI training clusters don't want to design at the ceiling, they want to design with reserve. Their internal specs reflect what they've learned from operating the largest optical networks on the planet: the headroom matters, the thermal reality matters, and margin at the module level is cheaper than margin at the network level.

4. Why AI Fabrics Punish Marginal TDECQ More Than Cloud Did

You could build a traditional cloud data center with optics scored right at the IEEE ceiling and barely notice. Cloud traffic is bursty, flows are numerous and small, and TCP absorbs retransmits invisibly. AI fabrics are none of these things. Four structural differences change the math.

Collective traffic saturates links simultaneously. An all-reduce during backpropagation runs at 85–97% sustained link utilization for minutes at a time across every link in the fabric. A degraded link becomes the straggler for the entire collective. The other GPUs wait for the slow one.

Lossless transport means a marginal link stalls a pod. AI fabrics use RoCEv2 over Ethernet or InfiniBand — both lossless. When a marginal link produces FEC-uncorrectable bursts, the switch asserts Priority Flow Control pause frames. Those pauses propagate backward through the Clos network, causing head-of-line blocking at every hop. A single hot transceiver can stall a 3,072-GPU pod.

Fat flows don't average out. Cloud ECMP hashes across thousands of small flows. AI has a small number of very large flows — a single tensor-parallel flow might be the only thing crossing a link. If that link is marginal, you don't statistically average it away. You see it.

Synchronous jobs restart hard. Published AI cluster engineering research documents training runs experiencing one interruption every three hours across multi-week campaigns, with roughly 8% of unexpected interruptions attributed to network switch and cable failures. Operators maintaining greater than 90% effective training time do so only with aggressive checkpoint automation built specifically for this failure mode.

5. The Temperature Factor

Every transceiver datasheet lists an operating temperature range — commonly 0°C to 70°C case. Inside that range, the module is supposed to meet spec. In practice, TDECQ is not constant across temperature. Laser threshold current rises, slope efficiency drops, wavelength drifts, and relative intensity noise worsens as the junction heats up. All four effects push TDECQ up.

Illustrative. TDECQ can drift 0.5–1.5 dB from bench test (25°C) to AI rack operating temperature (65°C case), depending on the module design.

The thermal envelope inside a real AI rack is not the bench. An NVIDIA DGX H100 server puts out roughly 11 kW of heat across 8 GPUs. A GB200 NVL72 rack puts out 120–140 kW. Switches at the top of these racks see intake air already warmed by the chassis below. On a normal day in a well-designed hot-aisle/cold-aisle facility, switch module case temperatures sit around 45–55°C. On a warm afternoon in a facility with a marginal chiller, they can hit 65°C. Inside the module, the laser junction runs another 20–25°C hotter than the case.

Published AI cluster engineering research noted a 1–2% diurnal throughput variation on a large-scale GPU training run — the midday temperature rise was slowing things down. At that scale, a small percentage is a large dollar figure. Thermal headroom in the optics is one of the levers operators can pull.

6. What's Changing in 2026: IEEE 802.3dj

The IEEE 802.3dj task force is finalizing the standard for 800G single-wavelength optics (200G per lane) and 1.6T pluggables. As of April 2026, Draft 3.0 is in Sponsor Association ballot with a target publication of mid-2026. Three changes in that draft matter for anyone specifying optics in the next 18 months.

The reference equalizer is changing. From a 5-tap feed-forward equalizer to a 15-tap FFE plus a 1-tap decision feedback equalizer. At 106.25 GBaud, the bandwidth-limited inter-symbol interference is severe enough that a 5-tap FFE simply cannot keep up. The new reference is closer to what Marvell and Broadcom's current-generation receive DSPs actually implement.

The TDECQ ceiling is tightening. The proposed 802.3dj DR/FR limit is 3.0 dB, down from 3.4 dB in earlier PAM4 standards. LR4 drops from 3.9 dB to 3.5 dB. This is the first TDECQ limit reduction since the metric was introduced in 2017, and it reflects the stronger reference equalizer — if the receiver is more capable, the transmitter is held to a correspondingly tighter standard.

Overshoot and RIN are tightening too. Overshoot drops from 22% to 12%. RIN-OMA tightens from −137 dB/Hz to −139 dB/Hz. Both changes reflect the reality that at 200G per lane, the analog tolerances shrink.

Related reading: Understanding TDECQ (original explainer) · The Complete Guide to Upgrading AI Data Centers from 400G to 800G · 800G Transceiver Validation Guide