Introduction
Clock recovery is the process of extracting timing information from a data stream to allow the receiver to decode the transmitted data. In ethernet communication, digital data is sent without the clock signal and therefore must be regenerated at the receiver, using the timing information from the data stream.
Higher data rate transceivers are equipped with Clock Data Recovery (CDR) to ensure the transmitted and received signals are synchronized for optimal transmission. In this article, we will discuss situations when CDR has to be bypassed in transceivers and how you can control CDR values in MSA registers.
Tx/Rx CDR Control in Transceiver
Tx/ Rx CDR Control (100G-LR4 H4A2016085 at 10.3Gbps)
In this example, we are running a 100G module with 4 lanes of 25G. Here, we changed the PHY to run at 10.3Gbps, instead of the usual 25Gbps. Most PHYs can do that, but when you run it, you get jitter like in the image above because the clock is not being regenerated (CDR not bypassed). The clock is supposed to lock on 25Gb/s, but now that the data rate is 10.3Gb/s, the clock tries to regenerate and leaves large jitters.
Key Takeaways
To bypass the CDR , there are two things to be checked: whether the CDR bypass function is supported in the transceiver and then change the 62 hex register to 00. Immediately, you can see the loss of lock. FF on A0.05, indicates transmitter, receiver CDR loss of lock (LOL), are all set.
A0(00).0x62 = 0x00 for Tx-CDR 4/3/2/1 & Rx-CDR 4/3/2/1 CDR all off
= 0xFF for CDR all on
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