1.6T Optical For Ai Data Centers: The Complete Technical Guide

1 Inside the Link: 212.5G PAM4 Lanes, FEC, and CMIS Management

A 1.6T module is defined by three architectural layers: the 224G-class electrical interface, the FEC scheme that makes 200G-per-lane optics viable, and the CMIS management plane. The walk below runs from the host connector to the management registers — the layers an engineer touches during bring-up. (Looking for data-center network architecture — scale-up, scale-out, and fabric design? That is Sections 11 and 12.)

The electrical layer. The host connects over 1.6TAUI-8 — eight lanes of 212.5 Gb/s PAM4 — specified electrically by the OIF CEI-224G family, which defines a reach class for each position a 224G signal appears in a system:

At the 53 GHz-class Nyquist frequencies involved, the host-to-module channel is far more impaired than at 100G per lane — which is why the standard makes link training mandatory.

ILT: link training at 200G per lane. IEEE P802.3dj introduces inter-sublayer link training (ILT) — a standardized, negotiated equalization and tuning handshake between sublayers during bring-up, defined in Annex 178B and mandatory for 200G-per-lane PHYs and attachment unit interfaces. In practice, ILT status registers are the first thing an engineer reads when a 1.6T link fails to train (Section 14).

The FEC layer. At 200G per lane, the raw optical error rate is too high for the legacy code alone, so 802.3dj defines an end-to-end concatenated architecture:

• Outer code: Reed-Solomon RS(544,514) — "KP4" — the code the industry has run since 100G per lane. Alone, it supports a pre-FEC bit error ratio (BER) up to about 2.4×10⁻⁴.
• Inner code: an extended Hamming(128,120) code applied inside the module DSP, working with a convolutional interleaver. Concatenated with KP4, it relaxes the optical pre-FEC BER target to about 4.8×10⁻³ — nearly twenty times more error tolerance — in exchange for added latency (Section 9).
• Two operating modes: RS-only for the optically easier, short-reach paths (lower latency), and concatenated inner-FEC for the harder ones. Post-FEC performance targets remain at the effectively error-free level modern RDMA fabrics require.

The optical layer: three viable technologies. Silicon photonics (SiPh) is the mainstream 1.6T platform — a shared continuous-wave laser feeds silicon modulators, easing the laser supply constraint and lowering power; the leading suppliers report high-volume SiPh yields. Indium-phosphide EMLs serve the highest-performance single-mode designs. 200G-per-lane GaAs VCSELs make short-reach multimode real (Section 3). Thin-film lithium niobate modulators are emerging behind these three. At OFC 2026, Coherent demonstrated 1.6T transceivers spanning all of these platforms with DSPs from three suppliers — the clearest public evidence that the 1.6T optical layer is multi-sourced.

The DSP layer. Two merchant DSP families dominate 2026 designs: Broadcom Sian3 (3nm, sub-23 W for a full 1.6T module, supporting both the 212.5 and 226.875 Gb/s line rates and the 802.3dj FEC modes; sampling March 2025, production from Q3 2025) and Marvell Ara (3nm, in mass volume, extended in March 2026 with linear-receive, reliability-focused, gearbox, and coherent-lite variants). The module classes built without a full DSP — LRO and LPO — are covered in Section 5.

The management layer. 1.6T modules implement CMIS 5.x — the register model through which hosts read module identity, configure the media interface, and poll digital diagnostics (temperature, supply voltage, transmit bias, transmit and receive optical power, and per-lane FEC counters). CMIS telemetry is the raw material of fleet-scale optics monitoring (Section 14). Current Vitex 1.6T designs implement CMIS 5.3. For linear modules, the emerging CMIS-VCS (Versatile Control Set) specification extends the register model with the host-to-module negotiation that LPO requires; OIF published the CMIS-VCS tutorial in March 2025 and demonstrated the interface at OFC 2026. (The latest published CMIS revision is 5.4, May 2026; the revision a given module implements is stated on its datasheet, and that revision — not the newest one — is what governs bring-up behavior.)

2 Form Factors: OSFP224, OSFP-XD, and QSFP-DD1600

Three pluggable form factors carry 1.6T, and they are not interchangeable. The selection logic is thermal envelope and ecosystem: OSFP224 is the volume AI-fabric choice, OSFP-XD is the high-power and 3.2T-headroom choice, and QSFP-DD1600 is the backward-compatibility choice.

IHS and RHS variants. The OSFP MSA defines two mechanical variants at every speed grade. IHS (integrated heat sink) modules carry their own heat sink for front-to-back airflow — the air-cooled switch standard. RHS (riding heat sink) modules have a flat top that mates against a host-provided heat sink or cold plate — the NIC-side and liquid-cooled standard, defined for 1.6T as RHS1600. The cages are keyed differently and the two are not interchangeable, though the optics on either side of a link interoperate normally. One compatibility fine point the MSA settles explicitly: backward compatibility is directional — an older OSFP or OSFP800 module operating in a new OSFP1600 port is a supported use case, while inserting an OSFP1600 module into a legacy OSFP/OSFP800 port is described by the MSA as not advisable, because mechanical tolerances, latching, contact integrity, and maximum-speed operation are not assured. Always qualify the exact host connector, cage, latch, airflow, and electrical interface. The 2026 mapping is straightforward: air-cooled switch cages take IHS; NIC cages and liquid-cooled systems take RHS (ConnectX-9 in OSFP uses the RHS cage, with QSFP112 as the alternative NIC option). Confirm the cage type alongside the module type when specifying.

Module types within OSFP. The MSA additionally defines module lengths and power classes; longer Type 2 housings accommodate higher-power designs. As a worked reference point from a published datasheet: the Vitex 1.6T DR8 (part number VO-1TDR8CM-AA) is built in an OSFP MSA Rev 5.22 Type 2 housing with an integrated heat sink, specified at 22 W typical and 23.8 W maximum over a 0–70 °C case-temperature range.

Connector gender. By long-standing industry convention, the MPO receptacles on parallel-optic modules are pinned (male), and the mating trunks and patch cords are unpinned (female). Ordering female-to-female cabling against pinned module ports is the default; verify against the specific module drawing when mixing vendors.

3 Module Types and Reach: DR8, DR8-2, 2×FR4, SR8, and Coherent

The complete 1.6T media map has six entries that matter, and only four of them are IEEE physical-medium-dependent (PMD) types. Knowing which is which prevents two common specification errors: expecting a standards designation that does not exist, and dismissing a de-facto module class that ships in volume.

What IEEE P802.3dj actually defines at 1.6T. The draft standard enumerates exactly four 1.6T PHY types: 1.6TBASE-KR8 (backplane), 1.6TBASE-CR8 (twinax copper), 1.6TBASE-DR8 (500 m parallel single-mode), and 1.6TBASE-DR8-2 (2 km parallel single-mode) — plus the electrical interfaces 1.6TAUI-8 (8×200G) and 1.6TAUI-16 (16×100G). There is no 1.6T FR or LR wavelength-multiplexed PMD in 802.3dj. Every duplex-fiber 1.6T optic on the market is therefore a multi-source-agreement or de-facto type built from standardized 800G engines.

Reading the map. DR8 is the volume workhorse — the 500 m parallel type that anchors leaf-to-GPU and leaf-to-spine links and reuses 800G fiber plant (Section 10). DR8-2 extends the same parallel wiring to 2 km and is a genuine IEEE PMD, which matters for multi-vendor procurement language. 2×FR4 delivers 2 km over just four fibers by construction — two independent 800G FR4 channels — and is the fiber-lean alternative where duplex-LC plant exists. Multimode at 1.6T is real at the component level (200G-per-lane VCSELs ship, and merchant DSPs integrate VCSEL drivers), but it is a de-facto class rather than an 802.3dj PMD, and its role is short-reach niches rather than the AI-fabric mainline. Single-engine FR8 and LR8 duplex designs at a full 1.6T remain MSA territory. Coherent 1600ZR-class optics for data center interconnect are a 2027-era deployment story: as of August 2026 the OIF's 1600ZR and 1600ZR+ Implementation Agreements remain active development projects (with 2026 completion targets), not yet published IAs, with a coherent-lite project trailing for the 20–40 km campus tier.

The full 802.3dj PMD ladder, for reference. The draft scales one pattern across four payload rates; the asymmetry worth remembering is that wavelength-multiplexed and coherent single-wavelength types exist at 800G but not at 1.6T.

Choosing Between DR8 and 2×FR4

The first real selection decision most teams face at 1.6T reduces to three variables: distance, fiber plant, and breakout intent.

Worked example 1 — 400 m row-to-row, existing 800G plant. A fabric team linking leaf switches to a GPU row 400 m away over trunks installed for 800G DR4 already owns MPO-12 APC infrastructure. DR8 on dual MPO-12 APC drops onto that plant's component set directly: same trunk type, same Method B polarity discipline, same panels — while consuming two 8-fiber paths per link, so the path inventory is the one number that must be re-verified. The published reference numbers for a shipping-class part: 500 m over single-mode, O-band (1304.5–1317.5 nm), CMIS 5.3 management, 22 W typical — with a 2×800GE breakout mode available over the two MPO-12 legs when one 1.6T-aggregate port must feed two 800G endpoints.

Worked example 2 — 1.4 km hall-to-hall, duplex plant. Linking aggregation between halls 1.4 km apart exceeds DR8 reach and would consume 16 fibers per link on parallel wiring. 2×FR4 covers 2 km on four fibers — two duplex-LC pairs — at 23.5 W typical, with silicon photonics doing the wavelength multiplexing. Where inter-hall duct space or leased-fiber counts are the constraint, the 4-versus-16 fiber difference is the entire decision. Where a 2 km parallel link is preferred for procurement-language reasons, DR8-2 is the IEEE-designated alternative at the same 16-fiber cost.

The general rule. Inside 500 m with MPO plant: DR8. Beyond 500 m, or wherever fiber count dominates: 2×FR4 (or DR8-2 where parallel wiring and an IEEE designation are required). Section 10 covers the plant details — MPO-12 versus MPO-16 wiring, polarity, and what an 800G plant carries forward — Section 12 places both types in full-fabric context, and breakout mechanics, copper and optical alike, are covered in full in Section 4.

4 1.6T Cables and Breakout: DAC, ACC, AEC, AOC, and 2×800G

Transceivers are only part of the 1.6T interconnect family. Copper cables, active optical cables, and breakout harnesses carry the first meters of every fabric — and at 1.6T, copper does not disappear; it compresses. Doubling the lane rate to 212.5G roughly halves what a passive cable can do, moves the active-copper classes to the center of in-rack design, and leaves optics for everything past a few meters. This section covers the full cable family, the breakout mechanisms that connect a 1.6T switch tier to an 800G host fleet, and — in one table — every product class that carries 1.6T, with the connector, pairing, and application each belongs to.

The three copper classes, and what 212.5G does to them. At 800G, the working figures are: passive DAC to about 2 m at zero added power; ACC (active copper cable, analog linear equalizers at each end) at 3–5 m and roughly 1.5–3 W per end; AEC (active electrical cable, DSP-retimed) to about 7 m — 9 m demonstrated — at roughly 7–12 W per end with field-proven reliability in the 100-million-hour MTBF class. At 212.5G per lane:

The first merchant 1.6T AEC DSP was announced in June 2024 (Marvell), extending copper reach roughly threefold at 200G-class lanes, and 16-lane 1.6T AEC designs date to 2022 (Credo, in OSFP-XD) — copper silicon is not the bottleneck. The engineering trade is unchanged from 800G, just shifted left: every meter that stays on copper avoids two optical transceivers, their power, and their failure modes. The 802.3dj copper PMDs — 1.6TBASE-CR8 for twinax cable and 1.6TBASE-KR8 for backplanes — standardize the electrical layer beneath all three classes, and breakout copper is covered with the other breakout mechanisms below.

Placement rule. GPU-to-ToR and adjacent-rack links: copper first, in DAC → ACC → AEC order of preference as distance grows. Past the AEC envelope: optics, per Section 3. The full decision framework, including where AOC fits between AEC and structured fiber, follows the logic of the 800G interconnect selection guide; current 1.6T-era copper parts are cataloged under AECs for AI data centers.

1.6T AOC: Active Optical Cables at 200G Per Lane

1.6T AOCs are real and shipping as a class, in two builds: multimode 2×SR4-style twin-engine designs, and parallel single-mode builds that extend the same idea to longer rows. An AOC bonds the optical engines permanently to the fiber, which changes the operational math rather than the physics: there are no field connectors to inspect or clean — the cleanliness discipline of Section 10 disappears at 1.6T's most failure-prone points — but the assembly fails as one unit and is replaced, not repaired, and its length is fixed at order time. That makes the AOC the row-scale answer (tens of meters, rack-to-rack) where a structured trunk-and-panel plant is not justified and copper cannot reach. Power sits between AEC and structured optics; published 800G-era AOC figures run 12–17 W per end, and 1.6T figures are design-dependent — read them off the specific assembly's datasheet rather than a class average. Selection order for the first meters of the fabric therefore stays simple: DAC, then ACC, then AEC, then AOC, then structured fiber with transceivers — each step buying reach with watts and serviceability trade-offs.

1.6T Breakout: One Cage, Two 800G Endpoints

Breakout is not a corner case at 1.6T — it is the standard host-connection pattern of the generation. Hosts remain at 800G-class ports through the Rubin era (Section 7), so the volume link of 2026–2027 is a 1.6T switch cage deliberately feeding two 800G endpoints. Three mechanisms deliver it, and they are not interchangeable:

• Copper breakout (in-rack). 1.6T-to-2×800G Y-cables — including IHS-to-RHS variants that connect a finned twin-port switch cage to two flat-top NIC cages — are standard parts of the 2026 rack, built on the same DAC/ACC/AEC electrical classes as straight cables and subject to the same reach compression.
• Optical breakout (the DR8 2×800GE mode). A dual-MPO DR8 module can run its two MPO-12 legs as two complete, independent 800G channels to two different endpoints. The mode is declared through CMIS and stated on vendor datasheets — including the Vitex VO-1TDR8CM-AA — and it works because the dual-MPO-12 wiring convention makes each leg a full 800G DR4-class path (Section 10). Reach follows the parent module class, to 500 m.
• Twin-port platform semantics. On Quantum-X800-class platforms the “breakout” is native: the twin-port module is two 800G links by construction, routed to two endpoints over two fiber paths (Section 6). Nothing is being split — the platform never presented a single 1.6T port in the first place.

Four working rules keep breakout deployments clean. Configure the port mode explicitly — a leg that stays dark because the port was left in native mode is the most common breakout bring-up failure (Section 14). Treat the two legs as two links in the polarity plan: each MPO-12 leg carries its own lane map, and crossed legs are the second most common failure. Where many small endpoints land on limited faceplate space, very-small-form-factor connectors — MDC, SN, SN-MT — appear at the far end of breakout harnesses (Section 10). And qualify breakout as breakout: a module validated only in native mode has not been validated for the deployment that will actually run (Section 14, stage 10). For planning mechanics, the 400G DR4 breakout planning guide scales directly to the 1.6T-to-2×800G case.

The 1.6T Interconnect Family, In One Table

Everything above — plus the transceiver classes of Section 3 — in a single reference. Form factors at 1.6T are the three of Section 2 (OSFP224 in volume, OSFP-XD, QSFP-DD1600) plus the non-pluggable CPO engine; the rows below are the product classes built in them. Statuses as of August 2026.

For where each class sits in a whole fabric — in-rack, NIC-to-leaf, leaf-to-spine, hall, campus, DCI — Section 12's Map 1 assigns the positions, Map 2 assigns cage and port semantics per ecosystem, and the reference-fabric worked examples live in Sections 6 and 7 (Quantum-X800 two-level fat tree; Tomahawk 6-class two-tier 128K-XPU scale-out).

5 Retiming Architectures: Fully Retimed, LRO, and LPO

Every 1.6T module belongs to one of three retiming architectures, and the industry uses at least eight names for them. The taxonomy below is exhaustive on purpose: the synonyms are the source of most confusion in datasheets and RFQs.

The 2026 state of play. The power ladder is the whole argument: cutting a 1.6T module from the ~23–25 W fully retimed class to ~16 W (LRO) or ~10 W (LPO) removes hundreds of watts per switch and megawatt-class totals per large fabric. The complication is thermal history and host dependency. The first fully linear 1.6T implementations ran above 30 W — the linear analog front ends were not yet efficient at 212.5G — which is why LRO is the deployable low-power path in 2026, with LPO maturing behind it; at OFC 2026, suppliers demonstrating 1.6T LPO consistently showed LRO variants alongside. Host support is the second gate: linear modules only work where the switch silicon is characterized to drive them — Broadcom Tomahawk-class ASICs and the systems built on them lead here, and Arista specifies LPO support across the 7060XE7 line with interconnect-power reductions cited in the 50–60 percent range. The electrical foundation is the OIF CEI-224G-Linear work and the LPO MSA's 200G-per-lane specification effort.

Interoperability rule of thumb. A fully retimed module tolerates host variation; a linear module inherits the host's equalization quality. Qualify LPO and LRO against the specific switch and NIC — never generically (Section 14). The complete decision framework, including when the power saving justifies the qualification burden, is in Vitex's LPO guide; current linear-class parts are cataloged under Linear Pluggable Optics.

6 Twin-Port Modules vs Native 1.6T Ports

This section settles one purchasing question: when a platform, a datasheet, and a quote all say "1.6T," are they describing the same link? On today's market they often are not — and the difference decides which module variant works, and how many endpoints one cage can feed.

On NVIDIA Quantum-X800 InfiniBand platforms, a "1.6T" module is a twin-port device that delivers two independent 800G links — not one native 1.6T port. Getting this distinction right decides which optics fit which cage, how breakout cabling is planned, and what "1.6T compatible" means on a purchase order.

How the Quantum-X800 is built. The Q3400 platform is a 4U InfiniBand XDR switch presenting 144 ports of 800G across 72 twin-port OSFP cages, for 115.2 Tb/s of aggregate, non-blocking bandwidth. It is the first switch generation built on 200G-per-lane SerDes, powered by the Quantum-3 ASIC, and its cages accept integrated-heat-sink (IHS) modules. A two-level fat tree of Q3400 switches connects up to 10,368 ConnectX-8 NICs. Each cage takes a twin-port OSFP224 module — physically a 1.6T-aggregate device running 8×200G electrical lanes — whose two engines terminate two separate 800G XDR links, routed to two different endpoints over two separate fiber paths.

The module classes. NVIDIA's twin-port family for this platform illustrates the pattern: the 2×DR4 class (dual MPO-12/APC, 1310 nm, 500 m, built on a 3nm 200G-per-lane DSP), with twin-port 2×FR4-class optics (dual duplex-LC, CWDM, 2 km) served by module suppliers in the same ecosystem. Flat-top / riding-heat-sink (RHS) counterparts of the same optics serve the NIC side, where ConnectX-9 uses the RHS cage (Section 2). The naming convention to internalize: twin-port 2×DR4 = 1.6T aggregate = two 800G ports.

Where native 1.6T ports actually live (August 2026). A native 1.6T port runs all eight lanes as one logical link. As of this writing, that capability ships or is dated on the Ethernet side: Broadcom Tomahawk 6 (shipping June 3, 2025; up to 64×1.6T native ports at 102.4 Tb/s), Arista 7060XE7-64PS/64PRS (announced June 9, 2026; 64 native 1.6T OSFP ports; air-cooled availability Q4 2026), and Marvell Teralynx T100 (102.4 Tb/s, sampling from Q2 2026). On the NVIDIA side there is, as of August 2026, no publicly documented native 1.6T pluggable port at either end: the ConnectX-9 SuperNIC's documented interfaces are an 800G-class OSFP port (its OSFP variant supports the RHS cage only) or dual QSFP112, and platform statements of "1.6 Tb/s per GPU" describe aggregate connectivity across those interfaces. The Rubin-era switch line splits by SKU between front-panel pluggables and co-packaged optics (Section 8).

7 Platforms and Production Status in 2026

As of mid-2026, 1.6T transceivers are in volume production at multiple suppliers — and which module type you buy is decided by which platform consumes it. The matrix below is the reference artifact for that decision: every shipping or dated 1.6T-era platform, the cage it presents, the module classes it takes, and its status. The durable pattern it documents: native 1.6T switching shipped first in the Broadcom Ethernet ecosystem, NVIDIA reached 1.6T through twin-port aggregation and then through co-packaged switch optics feeding hosts whose "1.6 Tb/s" is aggregate across 800G-class NIC ports, and every major merchant-silicon vendor now has a 102.4T-class part in flight. Entries are verified against primary sources as of August 24, 2026.

Who Is Deploying 1.6T, and Where It Lands First

The deployment pattern visible in mid-2026 has a clear shape. The switch tier moves first. Broadcom confirmed Tomahawk 6 shipping in production volume on March 12, 2026 — from initial samples to production deployment in under three quarters, a pace Broadcom itself called unprecedented for a chip of that scale — and its stated design target is AI fabrics beyond 100,000 XPUs, with a 128,000-XPU scale-out network fitting in two switch tiers. Named 1.6T systems now span the branded and open-networking markets: Arista's 7060XE7 line (endorsed publicly by Meta, Microsoft, and Oracle at announcement) and open-networking platforms such as Edgecore's AIS1600-64O, a 64×1.6T OSFP system announced in February 2026 for hyperscale AI clusters. Hosts follow a generation behind: the 2026 volume pattern is a native 1.6T or twin-port switch tier feeding 800G NICs (ConnectX-8 class) through 2×800G breakout, with hosts remaining at 800G-class ports through the Rubin generation — which keeps 2×800G breakout the standard host pattern rather than a stopgap. On the InfiniBand side, the same bandwidth arrives today as twin-port aggregate on Quantum-X800 (Section 6). And per the forecast data below, shipments are heavily weighted to Q4 2026 — the demand is real, but most of the fleet is still in qualification as of this writing, which is precisely the window in which supply is secured.

A third scope has also formed: scale-across. Since August 4, 2025, Broadcom has been shipping Jericho4, a deep-buffered Ethernet fabric router built to interconnect AI clusters across data centers — lossless RoCE over distances beyond 100 km, UEC-compliant, with a 3.2T HyperPort mode that aggregates four 800GE links into one logical port. Scale-across is where the coherent end of the 1.6T media map (Section 3) earns its place: 800G-class coherent optics serve it today, and the 1600ZR class arrives for it in 2027.

Platform Timeline and What Each Launch Means for Optics

Every optics decision has a date attached: which cages exist today, when the next ones arrive, and what each launch changes about the modules to buy. The timeline pairs each platform milestone with its optics consequence; entries are current as of August 2026.

The shipping-today baseline. NVIDIA Quantum-X800 with ConnectX-8 800G NICs remains the volume InfiniBand deployment through 2026. On the Ethernet side, Tomahawk 6 systems from the major ODMs are the native-1.6T baseline, with Cisco and other system vendors participating in the 1.6T era on their own silicon and platform schedules. Platform-by-platform optic mapping for the NVIDIA side — which module class each cage accepts — follows the method of the NVIDIA platform compatibility guide, extended to the cage rules in Sections 2 and 6.

1.6T Transceiver Shipment Forecast (2026–2030) and the Supply Constraint

Production crossed the volume threshold in the first half of 2026. Around OFC 2026 (Los Angeles, March 15–19), multiple optics suppliers stated that 1.6T modules were in mass production across fully retimed, linear-receive, and linear designs. And on March 9, 2026, one publicly traded US optics supplier disclosed its first volume 1.6T order — more than $200 million from a single hyperscale customer, with shipments, following product qualification, expected to begin early in Q3 2026 and complete in Q4.

The supply-side constraint, plainly. The binding constraint differs by module architecture: 200G-per-lane electro-absorption modulated laser (EML) availability for the highest-performance single-mode designs, continuous-wave laser and silicon-photonics capacity, DSP availability, packaging and test throughput, and qualified manufacturing capacity each gate a different part of the market. The most-cited squeeze is lasers: McKinsey's June 2025 analysis projected the EML supply that 1.6T transceivers depend on falling 30–40 percent short of demand through 2029, and in March 2026 NVIDIA announced strategic partnerships with Lumentum and Coherent — a $2 billion investment in each, paired with broader purchase, capacity, and R&D arrangements — to expand laser and photonics supply. Silicon photonics eases the squeeze because one shared laser feeds many lanes instead of one laser per lane (Section 1). What this means in practice: through 2026–2027, 1.6T supply is allocated, not simply ordered, and the qualification work started now is what secures the allocation later (Section 13).

One platform class above deliberately has no pluggable story at the switch face at all — that is where Section 8 picks up.

8 Co-Packaged Optics: Where Pluggables End and CPO Begins

Co-packaged optics moves the optical engine from the front-panel module onto the switch ASIC package — and at 1.6T, that move is no longer hypothetical. The full treatment of CPO architecture, benefits, and trade-offs is in the companion Co-Packaged Optics 2026 guide; this section covers only what CPO changes for 1.6T pluggable planning. (One vocabulary note before the platforms: near-packaged optics (NPO) — optical engines mounted on the host board beside the ASIC rather than on its package — sits between front-panel pluggables and CPO, and parts of the industry position it as a hedge while co-packaging matures; the qualification logic of this guide applies to it unchanged.)

Three CPO platforms are shipping or dated, and each one changes where pluggables live — not whether they exist (statuses as of August 2026):

Quote the CPO power case carefully. NVIDIA's engineering material describes per-1.6T-link power falling from roughly 25–30 W to roughly 9 W, with the optical engine at about 7 W versus about 20 W for a pluggable DSP path — while the headline efficiency multiplier varies between sources (3.5× in the launch newsroom material, 5× in developer material). Cite the specific figure, not a blend.

The strategic fact for pluggable buyers. In the NVIDIA Rubin generation, the switch-side optics go co-packaged while the host side stays pluggable on ConnectX-9 SuperNICs — 800G-class ports (RHS OSFP or QSFP112 cages), with "1.6 Tb/s" as the aggregate per host. On the Broadcom side, Tomahawk 6 and the systems built on it — including Arista's 7060XE7 — continue shipping pluggable-cage front panels at native 1.6T. The consequence: pluggable 1.6T demand concentrates on the NIC/host side of CPO fabrics and on the Broadcom-ecosystem switch market. CPO relocates the transceiver decision; it does not remove it — exactly as the CPO guide's through-line predicts.

9 Power, Cooling, and Latency Budgets

1.6T link design runs into two budgets. The thermal budget decides which module variant you can buy and cool at all. The latency budget decides which FEC mode and which retiming architecture you run. This section works through both. Neither is a rounding error at 1.6T: per-port module power roughly doubles versus 800G, and industry planning figures put transceivers at up to 40–50 percent of a fully loaded switch's thermal load.

Power by module class (published and vendor-stated figures, as of August 2026):

There is no single "air ceiling." Thermal feasibility is a module–cage–airflow–ambient–host qualification question, and the published examples above already span the low-20-watt class to 33.5 W on air-cooled hosts, while the OSFP MSA (Rev 5.22) defines OSFP1600 power classes up to 42.9 W — an envelope, not a promise that any given host can cool it. Plan against the host platform's qualified module power class and case-temperature limits, and read every power figure with its labels: typical or maximum, per module or per engine, IHS or RHS, direct-detect or coherent, and shipping product versus target versus demonstration.

Rack math. A 64-port native 1.6T switch on ~24 W fully retimed modules carries roughly 1.5 kW of optics alone; a 512×800G-scale CPO chassis avoids most of it, which is the entire CPO argument. On air, the limit is platform-qualified rather than universal — published air-cooled parts run from the low-20-watt class to 33.5 W max — but every row has its limit, and coherent-class power (32–40 W) lands on cold plates on most platforms.

The cooling ladder. Four rungs, each unlocking a higher module power. Which rung a row sits on decides which module variant — IHS, RHS, or none at all — goes on the purchase order.

The racks are already liquid — the switch row follows. The AI racks these fabrics serve are already liquid: NVIDIA's GB300 NVL72 and the Vera Rubin NVL72 generation are fully liquid-cooled rack-scale systems, publicly sized by system partners in the roughly 120–230 kW-per-rack range — densities at which air cooling is not a consideration for the rack, and increasingly not for the switch row beside it. Immersion is the exception, not the rule: standard pluggable transceivers contain free-space optical paths whose behavior changes when a dielectric fluid replaces air, and no mainstream 1.6T pluggable is immersion-rated as of August 2026; direct-to-chip cold plates and CPO, not immersion, are the 1.6T thermal answers. Where liquid is unavailable, LRO and LPO (Section 5) attack the same problem from the demand side — roughly halving optics heat instead of removing it faster.

Planning mechanics — airflow direction, faceplate budgets, and per-rack optics power worksheets — carry over from the 800G thermal and power planning guide; the IHS-versus-RHS mechanics are detailed in the OSFP IHS vs RHS selection guide.

The Latency Budget

A 1.6T link's added latency comes from three places — FEC, retiming, and the medium — and 802.3dj makes two of them configurable. The figures below are design-budget classes drawn from standards contributions and vendor engineering material; they are planning numbers, not datasheet guarantees, and per-implementation values vary.

FEC latency. The Reed-Solomon outer code alone contributes on the order of 100 nanoseconds of processing per hop. The concatenated inner-FEC path adds the Hamming code (small — low tens of nanoseconds) plus the convolutional interleaver, which dominates: with full interleaving, FEC-related delay budgets reach several hundred nanoseconds per hop. This is exactly why the standard allows the interleaver to be bypassed on the optically easier short-reach paths — a DR8 link running the RS-only mode keeps FEC latency near the ~100 ns class, while longer or harder paths pay the concatenated cost for the twenty-fold error-tolerance gain (Section 1).

Retiming latency. A DSP hop adds a small, fixed retiming delay each direction; linear modules (LPO, and the receive side of LRO) remove it. The saving per hop is small in absolute terms — single-digit to low-double-digit nanoseconds — but it compounds across the five to nine optical hops of a multi-tier fabric, and it is one of the three standing arguments for linear optics alongside power and cost.

Medium latency. Passive copper adds effectively nothing; AEC retimers add far less than an optical DSP path; fiber itself contributes ~5 ns per meter regardless of module type — which is why physical topology usually swamps module choice.

System reference point. Arista quotes the 7060XE7 at "from 840 ns" switch latency — a useful anchor for what a 1.6T-era single hop costs end to end. The design pattern for latency-sensitive fabrics is structural: fewer tiers (the 102.4T radix argument of Section 12), copper where reach allows, RS-only FEC mode on short optical paths, and linear modules where the hosts support them. Measurement methodology — where in the stack latency is defined and how to compare vendor claims — is covered in Latency in optical transceivers.

10 Fiber Plant: MPO-12 vs MPO-16, APC, and Polarity

The best-kept good news at 1.6T: the component choices of a properly built 800G single-mode plant carry forward. The capacity math does not — one dual-MPO 1.6T DR8 link consumes two 8-fiber DR4-style paths, so spare-path count, panel-port capacity, and loss budgets must be re-verified even when the materials are right. Three physical-layer decisions remain — connector strategy, endface polish, and polarity — and this section takes them in turn.

Dual MPO-12 versus single MPO-16. A DR8 link needs 16 fibers, and the industry wires it in two ways. The first convention is dual MPO-12 APC: two 12-fiber connectors per module, with eight fibers used in each. Its advantages are practical — it reuses the exact trunk type installed for 800G DR4, and it is what gives the module its 2×800G breakout capability, because each MPO-12 leg is a complete 800G channel that can run to a different endpoint. The second convention is a single MPO-16 APC connector carrying all 16 fibers. It halves the connector count and maximizes point-to-point density, but it requires a trunk type that an 800G-era plant does not have.

Both conventions are legitimate, and NVIDIA's own DR8 family spans both. The selection logic is simple: brownfield reuse and breakout intent favor dual MPO-12; greenfield point-to-point density favors MPO-16 (Section 13). For polarity, parallel MPO channels — MPO-12 and MPO-16 alike — commonly run Method B or modified Method B, with adapter orientation chosen to preserve both the Tx/Rx lane map and APC endface mating; Type C pair-flipped trunks belong to duplex-breakout designs and are not a default for straight parallel links. Trunk type, adapter orientation, patch cords, connector keys, and module pinout must be validated as one polarity system, end to end. Cabling-vendor design guidance for greenfield AI plants is to install 16-fiber trunking with spare capacity, so that both conventions — and future rates — are served without re-pulling.

APC polish. 1.6T links use APC (angled physical contact) connectors: the fiber endface is polished at an 8-degree angle, so that reflected light is directed out of the fiber path instead of traveling back toward the transmitter. This matters more at 212.5G per lane than it ever did before, because reflections that a 100G link could tolerate now consume error-rate margin the FEC needs. APC is therefore the standard on the parallel single-mode interfaces — DR-class modules terminate in MPO/APC. Duplex WDM interfaces are different: shipping 2×FR4-class modules terminate in duplex-LC/UPC, so the polish is taken from the exact module specification, never assumed — and APC must never be mated to UPC. The companion discipline is cleanliness: a contamination level that a 100G link forgave will take down a 212.5G lane, which is why endface inspection is a formal stage of qualification (Section 14) rather than a best practice.

The fiber arithmetic. Per link, DR8 and DR8-2 use 16 fibers, 2×FR4 uses four, and a future single-engine duplex type would use two. In breakout harnesses, very-small-form-factor connectors — MDC, SN, and SN-MT — appear at the far end when many smaller endpoints must land on limited faceplate space.

For trunk counting, polarity schemes, and link-budget worksheets, the 800G structured cabling guide applies to 1.6T with one addition — count two 8-fiber paths per DR8 link, and treat Method B as the parallel-channel default; polarity fundamentals are covered in Understanding polarity in MTP fiber cabling systems.

A DR8 Link Budget, Worked

The question every plant review ends with is whether a specific run of trunks, panels, and patches will close the link. The arithmetic below answers it from the published Vitex 1.6T DR8 datasheet (VO-1TDR8CM-AA); it is a datasheet-derived, first-order insertion-loss allowance — not a complete IEEE channel-compliance calculation — and formal compliance testing uses the full draft channel methodology (Section 14).

The datasheet defines both ends of the budget. The weakest transmitter the specification permits — a lane at the maximum allowed eye closure of TDECQ 3.4 dB — must launch at least −1 + 3.4 = +2.4 dBm OMAouter. The receiver, tested against an equally stressed eye, must work down to a stressed sensitivity of −0.9 dBm OMAouter at the 2.4×10⁻⁴ pre-FEC limit. The difference is the channel allowance:

Three practical readings follow. First, the budget is spent on connectors, not glass — at these reaches, fiber attenuation is nearly free and every additional mated pair costs as much as 875 m of fiber, which is why cross-connect-heavy designs fail margin reviews that simple panel-to-panel designs pass. Second, moving from the 0.35 dB low-loss connector class to the 0.50 dB standard class across four mates burns 0.6 dB of the 1.7 dB margin — the low-loss class is not a luxury at 212.5G. Third, the short-link direction is safe by design: the receiver's damage threshold is +5 dBm and its maximum average receive power (+4 dBm) equals the transmitter's maximum average launch, so a zero-loss patch cord does not overload the receiver. Treat the remaining margin as planning headroom, not guard band: it must still absorb measurement uncertainty and an engineering reserve, the connector count is an explicit assumption (four mated pairs here), and return loss and multipath interference are controlled separately by the APC discipline above.

11 Fabric Choice: 802.3dj Ethernet vs InfiniBand XDR

One physical generation serves two fabrics. Ethernet at 1.6T and InfiniBand XDR run the same 200G-per-lane technology — the same PAM4 signaling class, the same OSFP-family form factors, and in many cases the same optical hardware, which suppliers offer in Ethernet and InfiniBand variants of one design — though a dual-rate DSP does not by itself mean a finished module exposes both modes; the datasheet and its CMIS application codes decide. What separates them is a small set of concrete differences: the line rate (212.5 Gb/s per lane for Ethernet, 226.875 Gb/s for InfiniBand XDR), the transport behavior above the physical layer, and who governs the roadmap. That framing is worth holding onto, because it means the fabric decision changes how a module is configured and purchased far more than it changes which modules exist.

The Ethernet side. The defining document is IEEE P802.3dj, the project specifying 200G/400G/800G/1.6T Ethernet over copper and single-mode fiber at 200G per lane. Its status matters for procurement language: Draft 3.0 entered the initial IEEE Standards Association ballot in March 2026 (per the task force's January 2026 closing report), Draft 3.2's second SA recirculation ballot ran August 1–16, 2026 (per the July 2026 task-force agenda), and approval remains a late-2026 target with movement into early 2027 possible. Hardware ships ahead of approval for a defensible reason — the clauses that define modules (the PMD set, the FEC architecture, ILT) have been stable across recent drafts, exactly as they were at the equivalent stage of 800G. What makes 1.6T Ethernet an AI fabric rather than just a faster LAN is the transport work above it: the Ultra Ethernet Consortium's 1.0 specification (2025) adds the congestion control, packet spraying, and telemetry that large training clusters need, and the merchant switch silicon of Section 7 — Tomahawk 6, Teralynx T100 — ships UEC-compliant. The result is a multi-vendor ecosystem: multiple switch suppliers, multiple optics suppliers, and open transport.

The InfiniBand side. InfiniBand XDR is defined by the InfiniBand Trade Association and implemented, in practice, by one vendor's stack: NVIDIA Quantum-X800 switches with ConnectX-8 SuperNICs today (800G per port, twin-port 1.6T-aggregate modules at the switch — Section 6), moving to Quantum-X Photonics CPO switches with ConnectX-9 hosts (800G-class ports; 1.6 Tb/s aggregate per GPU) in the Rubin generation. Its strengths are the mirror image of Ethernet's: a single-vendor, tightly integrated fabric with in-network computing (SHARP) and the shortest path to the performance of NVIDIA's reference architectures.

How the choice actually gets made. In 2026 the decision is less about raw link speed — the physical layer is shared — and more about operating model. Organizations optimizing for time-to-train on NVIDIA reference designs deploy InfiniBand and inherit its optics choices. Organizations optimizing for multi-vendor sourcing, Ethernet operational tooling, and cost at scale build UEC-class Ethernet on the Broadcom-ecosystem switches. Both are legitimate; many large operators run both. The full decision framework is in InfiniBand vs Ethernet for AI clusters, with protocol fundamentals in the InfiniBand overview. For the optics buyer, the practical takeaway is reassuring: because both fabrics consume the same class of 200G-per-lane modules, plant design (Section 10) and qualification methodology (Section 14) survive the fabric decision intact.

One scope note: three scales, one home for pluggables. AI network design in 2026 uses three scope words. Scale-up is the memory-semantic domain inside a rack or pod — NVLink today, UALink as the open counterpart — running on copper backplanes and moving toward on-package optics; it is not a market for pluggable 1.6T modules. Scale-out is the rack-to-rack cluster fabric this guide covers — the leaf, the spine, and the NIC — and it is where pluggable 1.6T transceivers live. Scale-across is the newest tier: interconnecting whole AI facilities into one training domain, served by deep-buffered routers such as Broadcom's Jericho4 (shipping since August 2025, lossless RoCE beyond 100 km, 3.2T HyperPorts of aggregated 800GE) and, from 2027, by 1600ZR-class coherent pluggables (Section 3).

12 Selecting Optics by Application and Architecture

Module selection at 1.6T is a mapping exercise: fabric position sets the media type, ecosystem sets the cage and port semantics, and operator priorities set the retiming architecture. Run the three maps in that order and the parts list writes itself.

Map 1 — fabric position to media type.

Map 2 — ecosystem to cage and port semantics.

Map 3 — operator archetype to priorities.

The radix dividend. The strongest architecture-level argument for going to 1.6T is not per-port speed — it is tier count. A 102.4 Tb/s, 64×1.6T switch carries the bandwidth of two 800G-generation switches, and industry analysis of Tomahawk 6-class designs holds that a 128,000-XPU scale-out network fits in two switch tiers instead of three — fewer switches, fewer hops, simpler congestion control, and materially fewer optics. Before counting, fix the vocabulary: a physical module body can carry one or two optical engines; a logical port is what the switch OS presents; a link has two transceiver ends; and CPO replaces some pluggable ends with on-package engines. The counts below are module ends.

Optics Count and Power at Cluster Scale, Worked

For a simplified single-rail, nonblocking two-tier fabric with one same-rate optical host link per GPU, the arithmetic is mechanical: host-to-leaf contributes ~N links × two ends = 2N, and leaf-to-spine contributes another ~N equivalent links × two ends = 2N — approximately 4N module ends. Larger per-GPU multiples are real, but only when the topology explicitly adds rails, tiers, storage or front-end fabrics, redundancy, or breakout structure. All figures below are planning arithmetic, not specifications:

The pattern to carry: the multi-megawatt spread between retiming architectures — recovered purely by a module-class choice — is why hyperscalers qualify linear optics first (Section 5) and why the highest-radix switch tiers move to CPO (Section 8). The honest counterweight: every watt saved by a linear module is paid for in per-host qualification effort, which is the trade Section 14 prices.

The decision checklist. A specification that answers all eight questions is one a supplier can quote correctly the first time:

1. Link distance, per fabric position.
2. Fiber availability: MPO-12 reuse, MPO-16 greenfield, or duplex-LC.
3. Power and cooling budget: the row's qualified air envelope, or RHS on cold plate / liquid (Section 9).
4. Latency sensitivity, and whether the RS-only FEC mode is required (Section 9).
5. Host support for linear optics, if LPO or LRO is in scope (Section 5).
6. Breakout intent: native 1.6T end to end, or 1.6T-to-2×800G.
7. Sourcing policy: multi-vendor procurement favors IEEE PMDs and fully retimed classes.
8. Brownfield reuse versus greenfield build (Section 13).

Vitex's AI data center solutions catalog and the AI data centers industry page organize the shipping range along exactly these axes.

The breakout question. Every selection above should be made breakout-aware: one 1.6T cage can deliberately feed two 800G endpoints in copper or fiber, and that — not native end-to-end 1.6T — is the standard host link of the era. The mechanisms, working rules, and the full interconnect-family table are in Section 4; the platform semantics behind them are Section 6.

13 Migrating from 800G: Brownfield and Greenfield

Every 1.6T deployment is one of two projects: a brownfield upgrade of an 800G AI fabric, or a greenfield build that starts at 1.6T. They share physics and differ in sequence.

Stay at 800G or Move to 1.6T?

The short answer: move the switch tier to 1.6T when the radix math pays, move the hosts with the platform generation, and stay at 800G where air-cooling limits, laser allocation, or an 800G NIC fleet gate you. 800G remains the volume workhorse of 2026 — the analyst shipment data of Section 7 is dominated by it — and the two generations are designed to coexist: the same fabric runs a 1.6T switch tier into 800G hosts through breakout for years, not months.

Brownfield: what carries forward, what changes.

The staged pattern that works. Upgrade the switch tier first and run 1.6T-to-2×800G breakout as the bridge: the switch moves to native 1.6T (or twin-port aggregate) while the NIC fleet remains 800G, and ConnectX-8-class and ConnectX-9-class hosts coexist in the same hall through the transition. Constraints to plan against, in order of how often they bite: rack power headroom (the doubled optics load lands on rows already near limit), the platform's qualified air envelope (published parts run to 33.5 W on air, but every row has its own limit — and it still forces the RHS/liquid decision earlier than expected), qualification lead time (weeks per module-host combination, run per Section 14), and laser supply — with 1.6T EML shortfalls projected at 30–40 percent through 2029, allocation conversations belong at the start of the project, not the end. For a worked example of a staged, rail-optimized AI-fabric deployment at the prior generation, see the H100 SuperPOD optics case study — the same sequencing discipline applies at 1.6T.

Greenfield: the decisions that differ. A 1.6T-native build gets to choose: MPO-16 versus dual MPO-12 trunking (density versus breakout flexibility — Section 10; the conservative answer is 16-fiber trunks with spare fibers, serving both), liquid-ready switch rows from day one (Section 9), CPO versus pluggable at the switch tier (Section 8 — the answer today is CPO at the highest-radix switch tier, pluggable everywhere multi-vendor sourcing matters), and DCI provisioning sized for the 1600ZR class landing in 2027. The radix economics reward ambition: one 1.6T tier replaces two 800G tiers of aggregation, so for a greenfield 2026-onward AI build, skipping 800G at the switch tier and deploying 1.6T directly is a defensible baseline — provided the module allocation and the qualification calendar are secured first.

14 Testing and Validation in the AI Data Center

At 1.6T the acceptance philosophy changes: the question is no longer "is the link error-free?" but "how much FEC margin remains before it is not?" A 212.5G PAM4 lane operates near the FEC threshold by design, and published operator data explains the stakes — the published Llama 3 training analysis recorded 466 job interruptions across a 54-day run — 419 of them unexpected, of which roughly 35 were categorized as switch or cable failures, with the remainder spanning GPUs, memory, software, hosts, and NICs; separately, a 2026 reliability analysis estimated that a hypothetical fleet of ten million optics would experience a link flap somewhere roughly every 48 seconds under its stated failure-rate assumptions. The first figure is observed training data; the second is a model — they must not be blended, and together they argue the same discipline. Each flap stalls a collective operation and idles GPUs. Qualification exists to keep marginal links out of that fleet.

The qualification workflow. The stages below compress the practitioner sequence; each row names its hero measurement and tool class.

The thresholds that anchor stages 6–7 (802.3dj-era values — anchor acceptance specifications to the exact draft revision and FEC mode in force when the test plan is written):

The 224G tool ecosystem, dated. The measurement chain matured through late 2025 and early 2026: 1.6T Ethernet test platforms with native RHS-module and ILT support shipped in September 2025 (VIAVI ONE-1600ER class); 802.3dj optical and electrical transmitter-conformance software, 224G-capable sampling scopes, and the 120 GBd BERT class arrived in March 2026 (Keysight); and the OIF's OFC 2026 interoperability demonstration — 40 member companies across CEI-224G, CEI-448G, coherent, and co-packaging — established multi-vendor 224G interop publicly. On the fabric side, the everyday instruments are the platform's own: per-lane raw and effective BER counters, FEC histograms, and DDM polling through host tools.

Telemetry as the early-warning system. CMIS digital diagnostics carry the failure precursors: operator practice treats sustained transmit-bias-current drift above baseline as a weeks-ahead warning of degradation, and the Open Compute Project formalized this direction in October 2025 with an optics-reliability workstream and an enhanced-telemetry software specification for fleet-scale visibility. A complete 1.6T interoperability report states: per-lane optical results with measurement conditions (case temperature, pattern, calibration provenance), pre- and post-FEC BER with margin, the FEC mode, the exact module and host firmware versions, the port mode under test — including breakout — and the channel loss. A report missing any of these is an anecdote, not a qualification.

Common Bring-Up Failures and First Checks

Most 1.6T bring-up problems fall into six patterns. The table maps each symptom to its most frequent cause and the first diagnostic step — every one of them traceable to a stage of the workflow above.

Deep-dive companions: the AI data center optics validation and testing handbook (the full program-level methodology), How to measure TDECQ (stage 6 in depth), DDM values, thresholds, and troubleshooting (stage 11), and Qualification testing of a transceiver (the generic baseline this section extends to 200G per lane).

15 Beyond 1.6T: 3.2T, 448G Lanes, and the Co-Packaged Trajectory

The 1.6T generation is the last one whose successor is already visible in silicon. Three threads define what comes next, and all three were public by mid-2026.

400G per lane exists. Broadcom's Taurus (BCM83640) — the first 400G-per-lane optical DSP, built on 3 nm — was announced available on March 11, 2026, with mass production expected late 2026, alongside a 400G-per-lane EML demonstration; multiple suppliers showed 400G-per-lane optical engines at OFC 2026. The electrical side follows through OIF CEI-448G, whose framework work opened in late 2025 with the first project (chip-to-module VSR) launched behind it and interoperability demonstrations already staged. The open question is modulation — whether 448G lanes stay PAM4 at roughly 224 GBd or move to higher-order PAM — and its answer sets the difficulty of everything downstream. The consensus planning window — a forecast, not a commitment: 448G SerDes in 2027, 3.2T module volume around 2028, with the NVIDIA Feynman / ConnectX-10 generation on the same horizon per NVIDIA's public roadmap.

The form factors fork. 3.2T has two mechanical paths: OSFP-XD at 16×200G — the incremental route inside an existing MSA — and the XPO multi-lane pluggable (public debut March 2026, led by Arista with a founding membership spanning the optics and silicon industry that passed 100 companies within a month): a 12.8 Tb/s liquid-cooled module with an integrated cold plate rated to 400 W, targeting 204.8 Tb/s of front-panel bandwidth per rack unit — roughly four times OSFP density. XPO is a bet that the pluggable model survives the power curve by going liquid rather than going away.

Co-packaging keeps climbing. The durable trajectory this guide has traced — CPO at the top of the fabric, pluggables at the host and everywhere multi-vendor sourcing matters, linear optics eroding DSP power in between — extends through 3.2T. Analyst projections have linear and co-packaged approaches taking a large share of the highest tiers by 2028 while pluggable volume continues growing underneath, and roughly half of the coming 1.6T/3.2T unit wave is forecast to use 400G-per-lane optics. The planning conclusion is the one that has held for three generations: the pluggable transceiver does not get replaced; it gets repositioned — and the buyer's job remains matching each link to the right part, wherever that link now lives.

16 Reference: The 1.6T Working Vocabulary

Kept at the end on purpose: the guide above uses these terms in context, and this section exists for the reader who needs one of them pinned down precisely — or for onboarding a colleague to the 1.6T conversation in five minutes.

A 1.6T optical transceiver is a pluggable module that carries 1.6 terabits per second of aggregate throughput on eight electrical lanes of 200 Gb/s-class PAM4 signaling. It is the direct successor of the 800G generation, produced by doubling the per-lane rate rather than the lane count — the pattern the industry has now run three times: 8×50G gave 400G (data center volume from roughly 2020), 8×100G gave 800G (volume in 2023–2024), and 8×200G gives 1.6T (volume production from 2026). Inside the module, the eight electrical lanes are converted to optical lanes — retimed by a digital signal processor (DSP) in the conventional design, or driven linearly in the newer low-power designs — and carried over parallel fibers or wavelength-multiplexed pairs.

Why 212.5 Gb/s and not 200. "200G per lane" names the payload rate; the signaling rate on the wire is higher because forward error correction (FEC) and physical-coding overhead ride on top of the data. For Ethernet under IEEE P802.3dj, the per-lane line rate is 212.5 Gb/s (approximately 106.25 GBd of PAM4, two bits per symbol); for InfiniBand XDR the equivalent figure is 226.875 Gb/s (approximately 113.4 GBd). Both describe the same physical generation, and the leading 224G-class DSPs support both rates in one device. When a datasheet quotes 113.4375 GBd per optical channel, it is stating the upper, InfiniBand-aligned bound of this family.

The working vocabulary. The rest of this guide uses a small set of terms precisely; they are defined here once.

How this guide is organized. Sections 1 through 5 describe the module itself — its electronics, mechanics, media types, and cabling companions. Sections 6 through 9 place it in the platform ecosystem, including the twin-port distinction that decides what "1.6T" means on a purchase order. Sections 10 through 14 cover deployment: budgets, fiber plant, fabric choice, selection, migration, and validation. Section 15 looks past 1.6T, and this vocabulary closes the reference.